Field Programmable Gate Arrays (FPGA) is a rapidly evolving technology in the Application Specific Integrated Circuit (ASIC) area. Their increasing use in ASICs is due to the fact that they combine the flexibility of mask programmable gate arrays (MPGAs) with the convenience of field programmability.
A typical FPGA architecture consists of two-dimensional array of logic modules which can be selectively connected using a programmable interconnect structure as shown in FIG. 1. It has rows of logic modules interspersed with routing channels consisting of predefined tracks. The tracks are segmented and two adjacent segments can be connected by programming a horizontal antifuse.
In addition to the horizontal antifuses, there are cross-point antifuses which are used to make connections between the horizontal and the vertical tracks. Such an architecture has typically been based on a logic module which incorporates multiplexer (Mux) based logic design, as shown in FIG. 2. The output of each logic module is connected to a dedicated vertical segment. Other vertical segments just pass through the modules, serving as feed-through between channels.
The choice of logic module architecture and the method by which the modules are configured directly affects the usefulness and performance of an FPGA for a particular application. Performance depends mainly on the number of antifuses used and the critical path delay.
Each antifuse used increases both resistance and capacitance of a net, and depending on the technology used, these values can be detrimentally high. The delay of the critical path through a circuit depends on the number of logic levels used to implement it. If multiple levels of logic modules are used to implement a function, the critical path delay may increase. Clock distribution may also influence critical path delay. However, since dedicated paths are used for clock distribution, delay attributable to it will not be as significant as other signal delays.
The area required for one logic implementation in comparison to another depends on a combination of size and number of modules required, and on routing and programming resources available. A large complex logic module needs more physical area but can implement many logic functions, thus requiring a smaller total number of modules for a particular design. However, the logic modules may be underutilized, resulting in wasted logic gates. On the other hand, if the logic modules are too small and simple, many such modules will be required to implement a complex logic function, resulting in a large interconnection requirement. This requires a trade-off between the module size and the number of modules.
In addition, as the number of nets increase, routing becomes more involved. For a large number of nets, more channels, tracks, and feedthroughs may be required. More circuitry would also be required for programming the antifuses, all of which contribute to an increase in area.
It is thus desirable that the structure of a logic module should be that it can implement as many useful functions as possible using a single module.
The prior art module of FIG. 2 has eight inputs and one output, which is useful in implementing random logic, but may be inefficient for implementing a certain class of applications which require a frequent use of specific logic functions, such as would be used in a Digital Signal Processor.